1. Field
Embodiments of the present disclosure relate to a driver for a semiconductor memory such as a PRAM or ReRAM and a system including the same, and more particularly, to a driver for a semiconductor memory, which is capable of increasing a write speed by momentarily charging each memory cell with parasitic capacitance, and a system including the same.
2. Description of the Related Art
As the development of information and communication technology is accelerated, a device capable of using texts, voices, and images together and performing interactive communication has become more desirable. Such a device may include a semiconductor element capable of processing more information at a high speed. In order to improve the performance of a system that includes such a device, a memory element which is a core part of the system is desirable to increase in speed and integration degree and to reduce in power consumption. A conventional DRAM may include a cell that has a 1-Transistor/1-Capacitor structure. As the size of the cell shrinks, a process of fabricating a capacitor of the cell becomes more difficult, and thus a nonvolatile memory capable of replacing the conventional DRAM becomes more desirable.
Next-generation memories which are currently developed aim at realizing the high integration and low power consumption of DRAM, the non-volatility of flash memory, and a high-speed operation of SRAM. Representative examples of the next generation memories include PRAM (phase change RAM), NFGM (nano floating gate memory), ReRAM (resistance RAM), PoRAM (polymer RAM), and MRAM (magnetic RAM). Since those memories have parasitic capacitance existing in a cell and a wiring coupled to the cell, a write delay may occur due to the parasitic capacitance, and thus a write speed may be reduced.
According to a conventional current driving method for addressing the above issues, a charging current is momentarily fed back to pre-charge parasitic capacitance, thereby reducing a data driving time and increasing the write speed.
FIG. 1 is a circuit diagram of a semiconductor integrated circuit, which corresponds to FIG. 17 of US Patent Laid-open Publication No. 2010/0118591. The semiconductor integrated circuit includes a boost circuit 70 to supply a write current to a memory cell, in addition to a constant current source circuit 20. The semiconductor integrated circuit controls the magnitude of a spike current supplied from the boost circuit 70 according to a distance from the constant current source circuit 20 to a write target memory cell group. As the distance from the constant current source circuit 20 to the write target memory cell group increases, the spike current supplied from the boost circuit 70 is set to have a larger value.